The authors explore peculiarities of using of codes with summation of weight- ed data bits in organization of technical diagnosis systems. The article provides with a brief overview in the area of using of classical codes and weighted codes with summation for solving the tasks of digital systems technical diagnostics. The classification of codes with summation is given. The error detection characteris- tics in data vectors by weighted codes with summation are particularly analyzed by types (unidirectional, symmetrical and asymmetrical) and multiplicities. It is proved that weighted codes with summation, for which the operation of residue by previously fixed modulo is not used in formation, have the ability to identify any unidirectional distortions in data vectors. In addition, it is proved that weighted codes with summation can not have the uniform distribution of data vectors among check vectors, it means impossible to construct a weighted code with summation with a theoretical minimum of the total number of undetectable errors. An article presents a method of implementation of weighted codes with summation gene- rators based on the use of standard circuits of half-adder and adders. Examples of implementation of weighted code generators on multiplexers and programmable logic devices of CPLD class are given. Experimental researches of the weighed codes with summation on the organization of concurrent error detection systems based on them were conducted. The error detection properties of error detection at the outputs of check circuits are analyzed, as well as the characteristics of the complexity of the technical implementation of concurrent error detection systems. The advantages and disadvantages of using of weighted codes with summation, which are manifested in the organization of concurrent error detection systems, are considered.
technical diagnostics, digital systems, concurrent error detection systems, sum codes, Berger code, weighted code with summation
1. Ubar R. Design and Test Technology for Dependable Systems-on-Chip (Premier Reference Source) / R. Ubar, J. Raik, H.-T. Vierhaus. - Information Science Reference, Hershey - New York : IGI Global, 2011. - 578 p.
2. Rabochee diagnostirovanie bezopasnyh informacionno-upravlyayuschih si- stem / A. V. Drozd, V. S. Harchenko, S. G. Antoschuk, Yu. V. Drozd, M. A. Drozd, Yu. Yu. Sulima ; pod red. A. V. Drozda i V. S. Harchenko. - Har'kov : Nacional'- nyy aerokosmicheskiy universitet im. N. E. Zhukovskogo (HAI), 2012. - 614 s.
3. Kharchenko V. Green IT Engineering : Concepts, Models, Complex Systems Architectures / V. Kharchenko, Yu. Kondratenko, J. Kacprzyk // Springer Book series «Studies in Systems, Decision and Control». - 2017. - Vol. 74. - 305 p.
4. Parhomenko P. P. Osnovy tehnicheskoy diagnostiki (optimizaciya algoritmov diagnostirovaniya, apparaturnye sredstva) / P. P. Parhomenko, E. S. Sogomo- nyan. - M. : Energoatomizdat, 1981. - 320 s.
5. Lala P. K. Principles of Modern Digital Design / P. K. Lala. - New-Jersey : John Wiley & Sons, 2007. - 436 p.
6. Sogomonyan E. S. Samoproveryaemye ustroystva i otkazoustoychivye sistemy / E. S. Sogomonyan, E. V. Slabakov. - M. : Radio i svyaz', 1989. - 208 s.
7. Matrosova A. Yu. Algoritmicheskie metody sinteza testov / A. Yu. Matrosova. - Tomsk : Izd-vo TGU, 1990. - 206 s.
8. Sapozhnikov Val. V. Samoproveryaemye diskretnye ustroystva / Val. V. Sapozh- nikov, Vl. V. Sapozhnikov. - SPb. : Energoatomizdat, 1992. - 224 s.
9. Mikoni S. V. Obschie diagnosticheskie bazy znaniy vychislitel'nyh / S. V. Mi- koni. - SPb. : SPIIRAN, 1992. - 234 s.
10. Nicolaidis M. On-Line Testing for VLSI : State of the Art and Trends / M. Nicolaidis // Integration, the VLSI Journal. - 1998. - Vol. 26. - Issues 1-2. - Rp. 197-209.
11. Schiano L. Self-Checking Design, Implementation, and Measurement of a Controller for Track-Side Railway Systems / L. Schiano, C. Metra, D. Marino // IEEE Transactions on Instrumentation and Measurement. - 2003. - Vol. 52. - Issue 6. - Pp. 1722-1728.
12. Dobias R. FPGA Based Design of the Railway’s Interlocking Equipments / R. Dobias, H. Kubatova // Euromicro Symposium on Digital System Design (DSD 2004), 31 Aug. - 3 Sept. 2004, Rennes, France. - Rp. 467-473.
13. Dobias R. Dependability Evaluation of Real Railway Interlocking Device / R. Dobias, J. Konarski, H. Kubatova // 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 3-5 September 2008, Parma, Italy. - Rp. 228-233.
14. Theeg G. Railway Signalling & Interlocking / G. Theeg, S. Vlasenko. - DW Media Group GmbH. - Eurailpress, Hamburg, 1st Edition, 2009. - 448 p.
15. Vít P. Fault Tolerant Duplex System with High Availability for Practical Applications / P. Vít, J. Borecký, M. Kohlík, H. Kubátová // 17th Euromicro Conference on Digital System Design, 27-29 August 2014, Verona, Italy. - Rp. 320-325.
16. Borecký J. Parity Driven Reconfigurable Duplex System / J. Borecký, M. Kohlík, H. Kubátová // Microprocessors and Microsystems. - 2017. - Vol. 52. - Pp. 251- 260.
17. Efanov D. V. Funkcional'nyy kontrol' i monitoring ustroystv zheleznodo- rozhnoy avtomatiki i telemehaniki / D. V. Efanov. - SPb. : FGBOU VO PGUPS, 2016. - 171 s.
18. Sapozhnikov Val. V. Osnovy tehnicheskoy diagnostiki / Val. V. Sapozhnikov, Vl. V. Sapozhnikov. - M. : Marshrut, 2004. - 316 s.
19. Fujiwara E. Code Design for Dependable Systems : Theory and Practical Applica- tions / E. Fujiwara. - New jersey : John Wiley & Sons, 2006. - 720 p.
20. Piestrak S. J. Design of Self-Testing Checkers for Unidirectional Error Detecting Codes / S. J. Piestrak. - Wrocław : Oficyna Wydawnicza Politechniki Wrocłavskiej, 1995. - 111 p.
21. Efanov D. Generalized Algorithm of Building Summation Codes for the Tasks of Technical Diagnostics of Discrete Systems / D. Efanov, Val. Sapozhnikov, Vl. Sapozhnikov // Proceedings of 15th IEEE East-West Design & Test Symposium (EWDTSʼ2017), Novi Sad, Serbia, September 29 - October 2, 2017. - Pp. 365-371.
22. Sapozhnikov Val. V. Vzveshennye kody s summirovaniem dlya organizacii kontrolya logicheskih ustroystv / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov // Elektronnoe modelirovanie. - 2014. - T. 36. - № 1. - S. 59-80.
23. Sapozhnikov Val. V. Analiz svoystv kodov s summirovaniem vzveshennyh in- formacionnyh razryadov po obnaruzheniyu oshibok v sistemah funkcional'- nogo kontrolya logicheskih ustroystv / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov // Izvestiya Peterburgskogo universiteta putey soobscheniya. - 2015. - № 1. - S. 114-126.
24. Berger J. M. A Note on Error Detection Codes for Asymmetric Channels / J. M. Ber- ger // Information and Control. - 1961. - Vol. 4. - Issue 1. - Pp. 68-73.
25. Das D. Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits / D. Das, N.A. Touba // Proceedings of the 17th IEEE VLSI Test Symposium, USA, CA, Dana Point, April 25-29, 1999. - Rp. 370-376.
26. Das D. Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes / D. Das, N.A. Touba, M. Seuring, M. Gossel // Proceedings of IEEE 6th International On-Line Testing Workshop (IOLTW), Spain, Palma de Mallorca, July 3-5, 2000. - Rp. 171-176.
27. Sapozhnikov Val. Combinational Circuits Checking on the Base of Sum Codes with One Weighted Data Bit / Val. Sapozhnikov, Vl. Sapozhnikov, D. Efanov, D. Nikitin // Proceedings of 12th IEEE East-West Design & Test Symposium (EWDTSʼ2014), Kyev, Ukraine, September 26-29, 2014. - Pp. 126-136.
28. Efanov D. Sum Code Formation with Minimum Total Number of Undetectable Errors in Data Vectors / D. Efanov, Val. Sapozhnikov, Vl. Sapozhnikov, D. Nikitin // Proceedings of 13th IEEE East-West Design & Test Symposium (EWDTSʼ2015), Batumi, Georgia, September 26-29, 2015. - Pp. 141-148.
29. Efanov D. V. O svoystvah koda s summirovaniem v shemah funkcional'nogo kontrolya / D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i telemehanika. - 2010. - № 6. - S. 155-162.
30. Sapozhnikov Val. V. Klassifikaciya oshibok v informacionnyh vektorah si- stematicheskih kodov / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov // Izvestiya vuzov. Priborostroenie. - 2015. - T. 58. - № 5. - S. 333-343.
31. Sogomonyan E. S. Design of Self-Testing and On-Line Fault Detection Combinational Circuits with Weakly Independent Outputs / E. S. Sogomonyan, M. Gössel // Journal of Electronic Testing : Theory and Applications. - 1993. - Vol. 4. - Issue 4. - Pp. 267- 281.
32. Busaba F. Y. Self-Checking Combinational Circuit Design for Single and Unidirectional Multibit Errors / F. Y. Busaba, P. K. Lala // Journal of Electronic Testing : Theory and Applications. - 1994. - Vol. 5. - Issue 1. - Pp. 19-28.
33. Saposhnikov Val. V. A New Design Method for Self-Checking Unidirectional Combinational Circuits / Val. V. Saposhnikov, A. Morosov, Vl. V. Saposhnikov, M. Göessel // Journal of Electronic Testing : Theory and Applications. - 1998. - Vol. 12. - Issue 1-2. - Pp. 41-53.
34. Morosow A. Self-Checking Combinational Circuits with Unidirectionally Independent Outputs / A. Morosow, Val. V. Sapozhnikov, Vl. V. Sapozhnikov, M. Goessel // VLSI Design. - 1998. - Vol. 5. - Issue 4. - Pp. 333-345.
35. Matrosova A. Yu. Self-Checking Synchronous FSM Network Design with Low Overhead / A. Yu. Matrosova, I. Levin, S. A. Ostanin // VLSI Design. - 2000. - Vol. 11. - Issue 1. - Pp. 47-58.
36. Göessel M. New Methods of Concurrent Checking : Edition 1 / M. Göessel, V. Ocheret- ny, E. Sogomonyan, D. Marienfeld. - Dordrecht : Springer Science+Business Me- dia B. V., 2008. - 184 p.
37. Matrosova A. Pseudo-Exhaustive Testing of Sequential Circuits for Multiple Stuck-at Faults / A. Matrosova, E. Mitrofanov // Proceedings of 14th IEEE East-West Design & Test Symposium (EWDTSʼ2016), Yerevan, Armenia, October 14-17, 2016. - Pp. 533-536.
38. Efanov D. V. Usloviya obnaruzheniya neispravnosti logicheskogo elementa v kombinacionnom ustroystve pri funkcional'nom kontrole na osnove koda Bergera / D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i telemehanika. - 2017. - № 5. - S. 152-165.
39. Ostanin S. Self-Checking Synchronous FSM Network Design for Path Delay Faults / S. Ostanin // Proceedings of 15th IEEE East-West Design & Test Symposium (EWDTSʼ2017), Novi Sad, Serbia, September 29 - October 2, 2017. - Rp. 696-699.
40. Efanov D. V. Tri teoremy o kodah Bergera v shemah vstroennogo kontro- lya / D. V. Efanov // Informatika i sistemy upravleniya - 2013. - № 1. - S. 77-86.
41. Das D. Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes / D. Das, N.A. Touba // Journal of Electronic Testing : Theory and Applications. - 1999. - Vol. 15. - Issue 1-2. - Pp. 145-155.
42. Efanov D. V. Primenenie modul'nyh kodov s summirovaniem dlya postroe- niya sistem funkcional'nogo kontrolya kombinacionnyh logicheskih shem / D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i teleme- hanika. - 2015. - № 10. - S. 152-169.
43. Sapozhnikov Val. Modular Sum Code in Building Testable Discrete Systems / Val. Sapozhnikov, Vl. Sapozhnikov, D. Efanov // Proceedings of 13th IEEE East- West Design & Test Symposium (EWDTSʼ2015), Batumi, Georgia, September 26-29, 2015. - Pp. 181-187.
44. Sapozhnikov Val. V. Modul'nye kody s summirovaniem v sistemah funk- cional'nogo kontrolya. I. Svoystva obnaruzheniya oshibok kodami v infor- macionnyh vektorah / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efa- nov, M. R. Cherepanova // Elektronnoe modelirovanie. - 2016. - T. 38. - № 2. - S. 27-48.
45. Sapozhnikov Val. V. Modul'nye kody s summirovaniem v sistemah funkcio- nal'nogo kontrolya. II. Umen'shenie strukturnoy izbytochnosti sistem funk- cional'nogo kontrolya / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efa- nov, M. R. Cherepanova // Elektronnoe modelirovanie. - 2016. - T. 38. - № 3. - S. 47-61.
46. Berger J. M. A Note on Burst Detection Sum Codes / J. M. Berger // Information and Control. - 1961. - Vol. 4. - Issue 2-3. - Pp. 297-299.
47. Blyudov A. A. Postroenie modificirovannogo koda Bergera s minimal'nym chislom neobnaruzhivaemyh oshibok informacionnyh razryadov / A. A. Blyudov, D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Elektronnoe modeli- rovanie. - 2012. - T. 34. - № 6. - S. 17-29.
48. Yang S. Logic Synthesis and Optimization Benchmarks User Guide : Version 3.0 / S. Yang // Technical Report 1991-IWLS-UG-Saeyang, MCNC. - 44 p.
49. Sentovich E. M. SIS : A System for Sequential Circuit Synthesis / E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, Sangiovanni-A. Vincentelli // Electronics Research Laboratory, De- partment of Electrical Engineering and Computer Science, University of California, Berkeley, 4 May 1992. - 45 p.
50. Harris D. M. Digital Design and Computer Architecture / D. M. Harris, S. L. Harris. - Morgan Kaufmann, 2012. - 569 p.
51. Tyurin S. F. «Zelenaya» programmiruemaya logika : koncepciya i elementy reali- zacii dlya FPGA proektov / S. F. Tyurin, V. S. Harchenko // Sistemy obrabotki informacii. - 2013. - № 9. - S. 84-92.
52. Maxfield C. The Design Warrior’s Guide to FPGA’s : 1st Edition, Devices, Tools and Flows / C. Maxfield. - Boston : Newnes, 2004. - 542 p.
53. MAX II Device Handbook. - Altera Corporation, 2007. - 107 p.
54. Hahanov V. I. Proektirovanie i testirovanie cifrovyh sistem na kristallah / V. I. Hahanov, E. I. Litvinova, O. A. Guz'. - Har'kov : HNURE, 2009. - 484 s.
55. Navabi Z. Digital System Test and Testable Design : Using HDL Models and Architectures / Z. Navabi. - Springer Science+Business Media, LLC 2011. - 435 p.
56. Collection of Digital Design Benchmarks. - URL : http://ddd.fit.cvut.cz/prj/ Benchmarks.
57. Sapozhnikov Val. Method of Combinational Circuits Testing by Dividing its Out- puts into Groups and Using Codes, that Effectively Detect Double Errors / Val. Sa- pozhnikov, D. Efanov, Vl. Sapozhnikov, V. Dmitriev // Proceedings of 15th IEEE East-West Design & Test Symposium (EWDTSʼ2017), Novi Sad, Serbia, September 29 - October 2, 2017. - Pp. 129-136.
