The article covers the process of synthesis of asynchronous RS- and JK-fl ip-fl ops, as well as synchronous JK-fl ip-fl op as a fi nite-state machine. Particular attention is paid to modeling the operation of JK fl ip-fl op. The article presents two options of implementation of JK fl ip-fl op as a basic diagram using Multisim software and as a description using Verilog language.
RS-, JK-fl ip-fl ops, JK fl ip- fl op, synthesis of fl ip-fl ops, the theory of fi nite-state machines
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