CODES WITH SUMMATION OF ONE-BITS WITH RANDOM MODULES OF CALCULATION
Abstract and keywords
Abstract (English):
The fundamental issue in the problem of digital systems of automatic and automated control formation is the choice of architecture and diagnostic support. Often this choice is associated with tracking of the characteristics of sum faulttolerant codes. In this article the set of codes with summation of one-bits, including classical parity codes, Berger codes, Bose-Lin codes and other modular codes, as well as modifi ed sum codes, constructed using the calculation of the least nonnegative residue of data vector’s weight and special correction coeffi cients, are analyzed. The classifi cation of codes with summation of one-bits is offered, basic characteristics of known sum codes are indicated. The characteristics of modifi ed codes with summation of one-bits with random modules of calculation are investigated in detail. Basic limitations on the set of errors of various types (unidirectionally, symmetrical and asymmetrical) and multiplicities, detected by modifi ed sum codes, are noted. Basic patterns of error’s distribution by types and multiplicities are indicated in considered class of sum codes. The capacity of the set of modifi ed fault-tolerant codes with summation of one-bits with random modules of calculation is determined.

Keywords:
diskretnaya sistema, tehnicheskaya diagnostika, kod s summirovaniem, kod Bergera, modul'nyy kod s summirovaniem, modificirovannyy kod s summirovaniem, naimen'shiy neotricatel'- nyy vychet, harakteristiki obnaruzheniya oshibok
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References

1. Hamming R. W. Coding and Information Theory : 2 Sub Edition / R. W. Hamming. - New Jersey : Prentice-Hall, 1986. - 272 p.

2. McCluskey E. J. Logic Design Principles (with Emphasis on Testable Semicustom Circuits) / E. J. McCluskey. - New Jersey : Prentice-Hall, 1986. - 549 p.

3. Sogomonyan E. S. Samoproveryaemye ustroystva i otkazoustoychivye sistemy / E. S. Sogomonyan, E. V. Slabakov. - M. : Radio i svyaz', 1989. - 208 s.

4. Goessel M. Error Detection Circuits / M. Goessel, S. Graf. - L. : McGraw-Hill, 1994. - 261 p.

5. Abramovici M. Digital System Testing and Testable Design / M. Abramovici, M.A. Breuer, A. D. Friedman. - New Jersey : IEEE Press, 1998. - 652 p.

6. Fujiwara E. Code Design for Dependable Systems : Theory and Practical Applications / E. Fujiwara. - John Wiley & Sons, 2006. - 720 p.

7. Mikroprocessornaya centralizaciya strelok i signalov EBILock 950 / G. A. Kazimov, V. N. Aleshin, A. E. Derevyanko, S. V. Zolotareva, G. F. Lekuta, S. B. Platunov, A. V. Suraev, S. A. Hohlov, K. D. Hromushkin ; pod. red. G. D. Kazieva. - M. : Transizdat, 2008. - 368 s.

8. Lala P. K. Principles of Modern Digital Design / P. K. Lala. - New Jersey : John Wiley & Sons, 2007. - 419 p.

9. Mikroprocessornye sistemy centralizacii : uchebnik dlya tehnikumov i kolledzhey zheleznodorozhnogo transporta / Vl. V. Sapozhnikov, V. A. Kononov, S. A. Kurenkov, A. A. Lykov, O. A. Nasedkin, A. B. Nikitin, A. A. Prokof'ev, M. S. Tryasov ; pod red. Vl. V. Sapozhnikova. - M. : GOU «Uchebno-metodicheskiy centr po obrazovaniyu na zheleznodorozhnom transporte, 2008. - 398 s.

10. Ryan W. E. Channel Codes : Classical and Modern / W. E. Ryan, S. Lin. - Cambridge University Press, 2009. - 708 r.

11. Ubar R. Design and Test Technology for Dependable Systems-on-Chip (Premier Reference Source) / R. Ubar, J. Raik, H.-T. Vierhaus. - Information Science Refer- ence, Hershey - N. Y., IGI Global, 2011. - 578 p.

12. Rabochee diagnostirovanie bezopasnyh informacionno-upravlyayuschih sistem / A. V. Drozd, V. S. Harchenko, S. G. Antoschuk, Yu. V. Drozd, M. A. Drozd, Yu. Yu. Sulima ; pod red. A. V. Drozda i V. S. Harchenko. - Har'kov : Nacional'nyy aerokosmicheskiy universitet im. N. E. Zhukovskogo (HAI), 2012. - 614 s.

13. Parhomenko P. P. Osnovy tehnicheskoy diagnostiki (optimizaciya algoritmov diagnostirovaniya, apparaturnye sredstva) / P. P. Parhomenko, E. S. Sogomonyan. - M. : Energoatomizdat, 1981. - 320 s.

14. Piestrak S. J. Design of Self-Testing Checkers for Unidirectional Error Detecting Codes / S. J. Piestrak. - Wrocław : Oficyna Wydawnicza Politechniki Wrocłavskiej, 1995. - 111 p.

15. Touba N. A. Logic Synthesis of Multilevel Circuits with Concurrent Error Detection / N. A. Touba, E. J. McCluskey // IEEE Transaction on Computer-Aided Design of Integrated Circuits and System. - 1997. - Vol. 16, Jul. - Pp. 783-789.

16. Nicolaidis M. On-Line Testing for VLSI - A Compendium of Approaches / M. Nicolaidis, Y. Zorian // Journal of Electronic Testing : Theory and Applications. - 1998. - N 12. - Pp. 7-20.

17. Das D. Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits / D. Das, N.A. Touba // Proceedings of the 17th IEEE VLSI Test Symposium, USA, CA, Dana Point, April 25-29, 1999. - Rp. 370-376.

18. Matrosova A. Self-Checking Synchronous FSM Network Design with Low Overhead / A. Matrosova, I. Levin, S.A. Ostanin // VLSI Design. - 2000. - Vol. 11. - Issue 1. - Pp. 47-58.

19. Das D. Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes / D. Das, N. A. Touba, M. Seuring, M. Gossel // Proceedings of IEEE 6th Inter- national On-Line Testing Workshop (IOLTW), Spain, Palma de Mallorca, July 3-5, 2000. - Rp. 171-176.

20. Matrosova A. Survivable Self-Checking Sequential Circuits / A. Matrosova, I. Levin, S. Ostanin // Proceedings of 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2001), Oct. 24-26, San Francisco, CA, 2001. - Rp. 395-402.

21. Berger J. M. A Note on Error Detection Codes for Asymmetric Channels / J. M. Berger // Information and Control. - 1961. - Vol. 4. - Issue 1. - Pp. 68-73.

22. Mitra S., McCluskey E. J. Which Concurrent Error Detection Scheme to Shoose? / S. Mitra, E. J. McCluskey // Proceedings of International Test Conference, 2000, USA, Atlantic City, NJ, 3-5 October 2000. - Rp. 985-994

23. Gessel' M. Postroenie samotestiruemyh i samoproveryaemyh kombinacionnyh ustroystv so slabonezavisimymi vyhodami / M. Gessel', E. S. Sogomonyan // Avtomatika i telemehanika. - 1992. - № 8. - S. 150-160.

24. Busaba F. Y. Self-Checking Combinational Circuit Design for Single and Unidirectional Multibit Errors / F.Y. Busaba, P. K. Lala // Journal of Electronic Testing : Theory and Applications. - 1994. - Issue 5. - Rp. 19-28.

25. Göessel M. New Methods of Concurrent Checking : Edition 1 / M. Göessel, V. Ocheretny, E. Sogomonyan, D. Marienfeld. - Dordrecht : Springer Science + Business Media B. V., 2008. - 184 p.

26. Efanov D. V. Usloviya obnaruzheniya neispravnosti logicheskogo elementa v kombinacionnom ustroystve pri funkcional'nom kontrole na osnove koda Bergera / D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i telemehanika. - 2017. - № 5. - S. 152-165.

27. Sapozhnikov Val. Search Algorithm for Fully Tested Elements in Combinational Circuits, Controlled on the Basis of Berger Codes / Val. Sapozhnikov, Vl. Sapozhnikov, D. Efanov // Proceedings of 15th IEEE East-West Design & Test Symposium (EWDTS`2017), Novi Sad, Serbia, September 29 - October 2, 2017. - Rp. 99-108.

28. Sapozhnikov Val. V. Klassifikaciya oshibok v informacionnyh vektorah sistematicheskih kodov / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov // Izvestiya vuzov. Priborostroenie. - 2015. - T. 58. - № 5. - S. 333-343.

29. Efanov D. V. O svoystvah koda s summirovaniem v shemah funkcional'nogo kontrolya / D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i telemehanika. - 2010. - № 6. - S. 155-162.

30. Sapozhnikov Val. V. Predel'nye svoystva koda s summirovaniem / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov // Izvestiya Peterburgskogo universiteta putey soobscheniya. - 2010. - № 3. - S. 290-299.

31. Efanov D. V. Tri teoremy o kodah Bergera v shemah vstroennogo kontrolya / D. V. Efanov // Informatika i sistemy upravleniya - 2013. - № 1. - S. 77-86.

32. Slabakov E. V. Postroenie polnost'yu samoproveryaemyh kombinacionnyh ustroystv s ispol'zovaniem ostatochnyh kodov / E. V. Slabakov // Avtomatika i telemehanika. - 1979. - № 10. - C. 133-141.

33. Bose B. Systematic Unidirectional Error-Detection Sodes / B. Bose, D. J. Lin // IEEE Transaction on Computers, vol. C-34, Nov. 1985. - Rp. 1026-1032.

34. Kavousianos X. Novel TSC Checkers for Bose-Lin and Bose Codes / X. Kavousianos, D. Nikolos // Proceedings of the 3ed IEEE International On-Line Testing Workshop, July 6-8, 1998, Capry, Italy. - Rp. 172-176.

35. Das D. Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes / Das D., N.A. Touba // Journal of Electronic Testing : Theory and Applications. - 1999. - Vol. 15. - Issue 1-2. - Pp. 145-155.

36. Sapozhnikov Val. V. Modul'nye kody s summirovaniem v sistemah funkcional'nogo kontrolya. II. Umen'shenie strukturnoy izbytochnosti sistem funkcional'nogo kontrolya / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efa- nov, M. R. Cherepanova // Elektronnoe modelirovanie. - 2016. - T. 38. - № 3. - S. 47-61.

37. Aksenova G. P. Neobhodimye i dostatochnye usloviya postroeniya polnost'yu proveryaemyh shem svertki po modulyu dva / G. P. Aksenova // Avtomatika i telemehanika. - 1979. - № 9. - S. 126-135.

38. Aksenova G. P. O funkcional'nom diagnostirovanii diskretnyh ustroystv v usloviyah raboty s netochnymi dannymi / G. P. Aksenova // Problemy upravleniya. - 2008. - № 5. - S. 62-66.

39. Ghosh S. Synthesis of Low Power CED Circuits Based on Parity Codes / S. Ghosh, S. Basu, N.A. Touba // Proceedings of 23rd IEEE VLSI Test Symposium (VTS’05). - 2005. - Rp. 315-320.

40. Blyudov A. Properties of Code with Summation for Logical Circuit Test Organization / A. Blyudov, D. Efanov, Val. Sapozhnikov, Vl. Sapozhnikov // Proceedings of 10th IEEE East-West Design & Test Symposium (EWDTS`2012), Kharkov, Ukraine, September 14-17, 2012. - Rp. 114-117.

41. Sapozhnikov Val. Modular Sum Code in Building Testable Discrete Systems / Val. Sapozhnikov, Vl. Sapozhnikov, D. Efanov // Proceedings of 13th IEEE East-West Design & Test Symposium (EWDTS`2015), Batumi, Georgia, September 26-29, 2015. - Rp. 181-187.

42. Efanov D. V. Primenenie modul'nyh kodov s summirovaniem dlya postroeniya sistem funkcional'nogo kontrolya kombinacionnyh logicheskih shem / D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i telemehanika. - 2015. - № 10. - S. 152-169.

43. Sapozhnikov Val. V. Modul'nye kody s summirovaniem v sistemah funkcional'nogo kontrolya. I. Svoystva obnaruzheniya oshibok kodami v informacionnyh vektorah / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov, M. R. Cherepanova // Elektronnoe modelirovanie. - 2016. - T. 38. - № 2. - S. 27-48.

44. Blyudov A. A. Modificirovannyy kod s summirovaniem dlya organizacii kontrolya kombinacionnyh shem / A. A. Blyudov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i telemehanika. - 2012. - № 1. - S. 169-177.

45. Blyudov A. A. Postroenie modificirovannogo koda Bergera s minimal'nym chislom neobnaruzhivaemyh oshibok informacionnyh razryadov / A. A. Blyudov, D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Elektronnoe modelirovanie. - 2012. - T. 34. - № 6. - S. 17-29.

46. Efanov D. On the Problem of Selection of Code with Summation for Combinational Circuit Test Organization / D. Efanov, Val. Sapozhnikov, Vl. Sapozhnikov, A. Blyudov // Proceedings of 11th IEEE East-West Design & Test Symposium (EWDTS`2013), Rostov-on-Don, Russia, September 27-30, 2013. - Rp. 261-266.

47. Blyudov A. A. Kody s summirovaniem dlya organizacii kontrolya kombinacionnyh shem / A. A. Blyudov, D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i telemehanika. - 2013. - № 6. - S. 153-164.

48. Blyudov A. A. O kodah s summirovaniem edinichnyh razryadov v sistemah funkcional'nogo kontrolya / A. A. Blyudov, D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i telemehanika. - 2014. - № 8. - S. 131-145.

49. Sapozhnikov Val. V. Primenenie kodov s summirovaniem pri sinteze sistem zheleznodorozhnoy avtomatiki i telemehaniki na programmiruemyh logicheskih integral'nyh shemah / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov // Avtomatika na transporte. - 2015. - T. 1. - № 1. - S. 84-107.

50. Efanov D. On the Problem of Selection of Modified Code with Summation of On-Bits for Logical Devices Test / D. Efanov, Val. Sapozhnikov, Vl. Sapozhnikov, A. Bliudov // Radioelectronics & Informatics. - 2016. - Issue 4. - Pp. 23-29.

51. Sapozhnikov Val. V. Vybor modificirovannogo koda s summirovaniem edinichnyh informacionnyh razryadov dlya logicheskih ustroystv s izvestnoy topologiey / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov // Avtomatika na transporte. - 2017. - T. 3. - № 4. - S. 578-604.

52. Sapozhnikov Val. V. Effektivnyy sposob modifikacii kodov s summirovaniem edinichnyh informacionnyh razryadov / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov // Izvestiya vuzov. Priborostroenie. - 2017. - T. 60. - № 11. - S. 1020-1032.

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