CHECKING OF COMBINATIONAL CIRCUITS, BASED ON SUM CODES WITH ONE WEIGHTED DATA BIT
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Abstract (English):
During the development of safe and reliable management systems the concurrent error detection of a technical condition of logical units are commonly used. While organizing such systems the characteristic of 100 % detection of single faults at the outputs of the logical elements of the internal structure of the object under control should be provided. It is possible through using of several approaches: 1) duplication; 2) using of fault-tolerant codes without modifying the structures of objects under test; 3) using of fault-tolerant codes with modifi cation of the structure of objects under test. The selection of a code at the design stage of concurrent error detection system is a key factor, that infl uence on the basic characteristics of the system. The paper presents the results of the study of properties of the sum codes with one weighted data bit. Proposed codes, as well as classical Berger codes, detect 100 % of unidirectional errors in the data vectors which means that they can be applied to solve similar tasks of technical diagnostics as Berger codes. Moreover, new codes have a reduced, in comparison with Berger codes, number of so-called symmetric errors. In this case, however, the weighting of a bit results into appearance of a certain number of asymmetric errors. The article provides conditions of formation of the weight-based sum code that is capable of a 100 % detection of errors of odd multiples and unidirectional errors in data vectors. In addition, the article defi nes new characteristics of sum codes with one weighted data bit, the tracking of which in practice will allow to organize a concurrent error detection systems for logic units devices with improved performance.

Keywords:
technical diagnostics, concurrent error detection system, sum code, Berger code, bit weight, sum weight-based code, undetectable error in data vector, error detecting properties
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