For design of modern railway automation and remote control systems increasingly the microelectronics and microprocessor techniques are used, including field-programmable gate arrays (FPGA). This article describes an approach to the development of fault-tolerant automation systems with built-in concurrent error detection means. Concurrent error detection system is proposed to be formed on the basis codes with summation of on-bits. The article describes the characteristics of on-bit sum codes for detection of different types of errors at the outputs of the arithmetic logic units of FPGA.
railway automation and remote control, reliability, safety, concurrent error detection (CED) system, sum codes, Berger code, modifi ed Berger code, data bits, undetectable error
1. Stancionnye sistemy avtomatiki i telemehaniki : ucheb. dlya vuzov zh.-d. trans-porta / Vl. V. Sapozhnikov, B. N. Elkin, I. M. Kokurin i dr. ; pod red. Vl. V. Sapozhnikova. - Moskva : Transport, 1997. - 432 s.
2. Nikitin A. B. Tendencii razvitiya elektricheskoy centralizacii i komp'yuternyh sistem operativnogo upravleniya dvizheniem poezdov na stanciyah / A. B. Nikitin, S. V. Bushuev // Transport Urala. - 2006. - № 2. - S. 14-18.
3. Mikroprocessornye sistemy centralizacii : uchebnik dlya tehnikumov i kolledzhey zheleznodorozhnogo transporta / Vl. V. Sapozhnikov, V. A. Kononov, S. A. Kurenkov, A. A. Lykov, O. A. Nasedkin, A. B. Nikitin, A. A. Prokof'ev, M. S. Tryasov ; pod red. Vl. V. Sapozhnikova. - Moskva : GOU «Uchebno-metodicheskiy centr po obrazovaniyu na zheleznodorozhnom transporte», 2008. - 398 s.
4. Theeg G., Vlasenko S. Railway Signalling & Interlocking - International Compendium, Eurailpress, 2009, 448 p.
5. Kornienko A. A. Intellektual'nye komp'yuternye sistemy operativnogo upravleniya dvizheniem poezdov na stanciyah / A. A. Kornienko, A. B. Nikitin, A. D. Homonenko // Izvestiya Peterburgskogo universiteta putey soobscheniya. - 2012. - № 2. - S. 116-119.
6. Kononov V. A. Osnovy proektirovaniya elektricheskoy centralizacii promezhutochnyh stanciy : ucheb. posobie / V. A. Kononov, A. A. Lykov, A. B. Nikitin. - Moskva : FGBOU «Uchebno-metodicheskiy centr po obrazovaniyu na zheleznodorozhnom transporte», 2013. - 348 s.
7. Analiz sostoyaniya bezopasnosti dvizheniya poezdov, nadezhnosti raboty sistem i ustroystv ZhAT v hozyaystve avtomatiki i telemehaniki v 2013 godu / OAO «Rossiyskie zheleznye dorogi», Upravlenie avtomatiki i telemehaniki Central'noy direkcii infrastruktury. - Moskva, 2014. - 174 s.
8. Sapozhnikov V. V. Teoreticheskie osnovy zheleznodorozhnoy avtomatiki i telemehaniki : uchebnik dlya vuzov zh.-d. transporta / Val. V. Sapozhnikov, Yu. A. Kravcov, Vl. V. Sapozhnikov ; pod. red. Val. V. Sapozhnikova. - Moskva : GOU «Uchebno-metodicheskiy centr po obrazovaniyu na zheleznodorozhnom transporte», 2008. - 394 s.
9. Gavzov D. V. Metody obespecheniya bezopasnosti diskretnyh sistem / D. V. Gavzov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i telemehanika. - 1994. - № 8. - S. 3-50.
10. Lisenkov V. M. Statisticheskaya teoriya bezopasnosti dvizheniya poezdov / V. M. Lisenkov. - Moskva : VINITI RAN, 1999. - 322 s.
11. Lisenkov V. M. Celi, principy i metody tehnicheskogo regulirovaniya na zheleznodorozhnom transporte / V. M. Lisenkov // Transport Rossiyskoy Federacii. - 2009. - № 5. - S. 42-45.
12. Lach J., Mangione-Smith W. H., Potkonjak M. Low Overhead Fault-Tolerant FPGA Systems, IEEE Transactions on Very Scale Integration (VLSI) Systems, 1998, vol. 6, issue 2, pp. 212-221.
13. Uvarov S. S. Proektirovanie rekonfiguriruemyh otkazoustoychivyh sistem na plis s rezervirovaniem na urovne yacheek / S. S. Uvarov // Avtomatika i telemehanika. - 2007. - № 9. - S. 176-189.
14. Navabi Z. Digital System Test and Testable Design: Using HDL Models and Architectures, Springer Science+Business Media, LLC 2011, 435 p.
15. Ubar R., Raik J., Vierhaus H.-T. Design and Test Technology for Dependable Systems-on-Chip (Premier Reference Source), Information Science Reference, Hershey, N. Y., IGI Global, 2011, 578 p.
16. Chandra V., Verma M. R. A Fail-Safe Interlocking System for Railways, IEEE Design & Test of Computers, 1991, vol. 8, issue 1, pp. 58-66.
17. Chandra V., Kumar K. V. Reliability and Safety Analysis of Fault Tolerant and Fail-Safe Node for Use in Railway Signalling System, Elsevier Journal on Reliability Engineering and system, 1997, vol. 57, issue 2, pp. 177-183.
18. Dobiáš R., Kubátová H. FPGA Based Design of Railway’s Interlocking Equipment, Proceedings of EUROMICRO Symposium on Digital System Design, 2004, pp. 467-473.
19. Kubalík P., Fišer P., Kubátová H. Fault Tolerant System Design Method Based on Self-Checking Circuits, Proceeding of 12th International On-Line Testing Symposium 2006 (IOLTS’06), Lake of Como, Italy, pp.185-186.
20. Salewsky F., Taylor A. Fault Handing in FPGAs and Microcontrollers in Safety-Critical Embedded Applications: A Comparative Survey. Proceedings of 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD`2007), 2007, pp. 124-131.
21. Dobiáš R., Konarski J., Kubátová H. Dependability Evaluation of Real Railway Interlocking Device, Proceedings of 11th Euromicro Conference on Digital System Design. Los Alamitos, IEEE Computer Society, 2008, pp. 228-233.
22. Sasaki E., Hondo S., Ebuchi T. SAINT Integrated Signaling System with High Reliability and Safety, Hitachi Review, 2008, vol. 57, issue 1, pp. 41-45.
23. Chakraborty A. Fault Tolerant Fail Safe System for Railway Signalling, Proceedings of the World Congress on Engineering and Computer Science (WCECS 2009), USA San Francisco, vol. II, October 20-22, 2009.
24. Kabeckiy A. G. Metody i instrumental'nye sredstva postroeniya logicheskih ustroystv elektricheskoy centralizacii na baze programmiruemyh logicheskih integral'nyh shem / A. G. Kabeckiy, D. S. Markov // Izvestiya Peterburgskogo universiteta putey soobscheniya. - 2010. - № 2. - S. 168-173.
25. Yildirim U., Durmuş M. S., Söylemez M. T. Fail-Safe Signalization and Interlocking Design for a Railway Yard: An Automation Petri Net Approach, Procedings of 7th International Symposium on Intelligent and Manufacturing Systems (IMS 2010), Sarajevo, Bosnia Herzegovina, September 15-17, 2010, pp. 461-470.
26. Parhomenko P. P. Osnovy tehnicheskoy diagnostiki (optimizaciya algoritmov diagnostirovaniya, apparaturnye sredstva) / P. P. Parhomenko, E. S. Sogomonyan. - Moskva : Energoatomizdat, 1981. - 320 s.
27. Nicolaidis M., Zorian Y. On-Line Testing for VLSI - A Compendium of Approaches, Journal of Electronic Testing: Theory and Applications, 1998, issue 12, pp. 7-20.
28. Jha N. K. Totally Self-Checking Checker Designs for Bose-Lin, Bose and Blaum Codes. IEEE Trans. Computer-Aided Design, vol. CAD-10, February 1991, pp. 136-143.
29. Touba N. A., McCluskey E. J. Logic Synthesis of Multilevel Circuits with Concurrent Error Detection, IEEE Trans. Computer-Aided Design of Integrated Circuits and System, vol. 16, July 1997, pp. 783-789.
30. Sapozhnikov Val. V. Osnovy tehnicheskoy diagnostiki / Val. V. Sapozhnikov, Vl. V. Sapozhnikov. - Moskva : Marshrut, 2004. - 318 s.
31. Fujiwara E. Code Design for Dependable Systems: Theory and Practical Applications, New Jersey: John Wiley & Sons, 2006, 720 p.
32. Lala P. K. Self-Checking and Fault-Tolerant Digital Design, University of Arkansas, 2001, 216 p.
33. Sogomonyan E. S. Samoproveryaemye ustroystva i otkazoustoychivye sistemy / E. S. Sogomonyan, E. V. Slabakov. - Moskva : Radio i svyaz', 1989. - 208 s.
34. Sapozhnikov Val. V. Samoproveryaemye diskretnye ustroystva / Val. V. Sapozhnikov, Vl. V. Sapozhnikov. - Sankt-Peterburg : Energoatomizdat, 1992. - 224 s.
35. Busaba F. Y., Lala P. K. Self-Checking Combinational Circuit Design for Single and Unidirectional Multibit Errors, Journal of Electronic Testing: Theory and Applications, 1994, issue 5, pp. 19-28.
36. Morosow A, Saposhnikov V. V., Saposhnikov Vl. V., Goessel M. Self-Checking Combinational Circuits with Unidirectionally Independent Outputs, VLSI Design, 1998, vol. 5, issue 4, pp. 333-345.
37. Saposhnikov V. V., Morosov A., Saposhnikov Vl. V., Göessel M. A New Design Method for Self-Checking Unidirectional Combinational Circuits, Journal of Electronic Testing: Theory and Applications, 1998, vol. 12, issue 1-2, pp. 41-53.
38. Sapozhnikov Val. V. Metod postroeniya kombinacionnyh samoproveryaemyh ustroystv s obnaruzheniem vseh odinochnyh neispravnostey / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, M. Gessel', A. A. Morozov // Elektronnoe modelirovanie. - 1998. - T. 20, № 6. - S. 70-80.
39. Matrosova A. Yu., Levin I., Ostanin S. A. Self-Checking Synchronous FSM Network Design with Low Overhead, VLSI Design, 2000, vol. 11, issue 1, pp. 47-58.
40. Berger J. M. A Note on Error Detecting Codes for Asymmetric Channels, Information and Control, 1961, vol. 4, issue 1, pp. 68-73.
41. Blyudov A. A. Postroenie modificirovannogo koda Bergera s minimal'nym chislom neobnaruzhivaemyh oshibok informacionnyh razryadov / A. A. Blyudov, D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Elektronnoe modelirovanie. - 2012. - T. 34, № 6. - S. 17-29.
42. Efanov D. V. O svoystvah koda s summirovaniem v shemah funkcional'nogo kontrolya / D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i telemehanika. - 2010. - № 6. - S. 155-162.
43. Sapozhnikov Val. V. Predel'nye svoystva koda s summirovaniem / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov // Izvestiya Peterburgskogo universiteta putey soobscheniya. - 2010. - № 3. - S. 290-299.
44. Efanov D. V. Primenenie koda s summirovaniem v sistemah tehnicheskoy diagnostiki i monitoringa ustroystv zheleznodorozhnoy avtomatiki i telemehaniki : dis. … kand. tehn. nauk / D. V. Efanov. - Sankt-Peterburg, 2010. - 192 s.
45. Sapozhnikov Val. V. Primenenie kodov Bergera i Hemminga v shemah funkcional'nogo kontrolya / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov, A. A. Blyudov // Izvestiya Peterburgskogo universiteta putey soobscheniya. - 2013. - № 2. - S. 168-182.
46. Efanov D., Sapozhnikov V., Sapozhnikov Vl., Blyudov A. On the Problem of Selection of Code with Summation for Combinational Circuit Test Organization, Proceedings of 11th IEEE East-West Design & Test Symposium (EWDTS`2013), Rostov-on-Don, Russia, September 27-30, 2013, pp. 261-266.
47. Sapozhnikov Val. V. Ob ispol'zovanii svoystv kodov s summirovaniem po obnaruzheniyu monotonnyh oshibok v sistemah funkcional'nogo kontrolya kombinacionnyh shem / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov // Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitel'naya tehnika i informatika. - 2014. - № 3. - S. 76-88.
48. Slabakov E. V. Samoproveryaemye vychislitel'nye ustroystva i sistemy (obzor) / E. V. Slabakov, E. S. Sogomonyan //Avtomatika i telemehanika. - 1981. - № 11. - S. 147-167.
49. Bose B., Lin D. J. Systematic Unidirectional Error-Detection Codes, Proceedings of IEEE Trans. Comput. 1985, vol. C-34, November, pp. 1026-1032.
50. Piestrak S. J. Design of Self-Testing Checkers for Unidirectional Error Detecting Codes, Wrocław: Oficyna Wydawnicza Politechniki Wrocłavskiej, 1995, 111 p.
51. Kavousianos X., Nikolos D. Novel TSC Checkers for Bose-Lin and Bose Codes, Proceedings of 3ed IEEE Int. On-Line Testing Workshop, July 6-8, 1998, Capry, Italy, rr. 172-176.
52. Das D., Touba N. A. Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes, Journal of Electronic Testing: Theory and Applications, 1999, vol. 15, issue 1-2, pp. 145-155.
53. Ghosh S., Basu S., Touba N.A. Synthesis of Low Power CED Circuits Based on Parity Codes, Proceedings of 23rd IEEE VLSI Test Symposium (VTS’05), 2005, pp. 315-320.
54. Blyudov A. A. On the Synthesis of Test Equipment for Modulo Codes with Summation, Proceedings of Petersburg Transport University, 2013, № 1, pp. 53-58.
55. Blyudov A. A. Kody s summirovaniem dlya organizacii kontrolya kombinacionnyh shem / A. A. Blyudov, D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i telemehanika. - 2013. - № 6. - S. 153-164.
56. Efanov D., Sapozhnikov V., Sapozhnikov Vl., Blyudov A. On the Problem of Selection of Code with Summation for Combinational Circuit Test Organization, Proceedings of 11th IEEE East-West Design & Test Symposium (EWDTS`2013), Rostov-on-Don, Russia, September 27-30, 2013, pp. 261-266.
57. Blyudov A. A. Issledovanie modificirovannyh kodov s summirovaniem v sistemah tehnicheskoy diagnostiki i obrabotki informacii v ustroystvah zhelezno- dorozhnoy avtomatiki i telemehaniki : dis. … kand. tehn. nauk / A. A. Blyudov. - Sankt-Peterburg, 2013. - 230 s.
58. Blyudov A. A. O kodah s summirovaniem edinichnyh razryadov v sistemah funkcional'nogo kontrolya / A. A. Blyudov, D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i telemehanika. - 2014. - № 8. - S. 131-145.
59. Yang S. Logic Synthesis and Optimization Benchmarks User guide: Version 3.0, Technical report Microelectronics Center of North Carolina, P. O. Box 12889, Research Triangle Park, NC 27709, January 15, 1991, 44 p.
60. Benchmarks: LGSynth89. - URL : http://www.cbl.ncsu.edu:16080/benchmarks/LGSynth89/mlexamples.
61. Gopalakrishan P., Rutenbar R. A. Direct Transistor-Level Layout for Digital Blocks, Boston, Kluwer Academic Pubishers, 2004, 125 p.
