The article describes the systematic code, that can be effectively used for organizing the concurrent error detection systems for combinational logic circuits. This systematic code belongs to the class of codes with summation of weighted data bits and has a simple rules of formation, that, respectively, provides a simple structure of encoding hardware. The above mentioned systematic code has the same number of check bits as a classic Berger code, however, it has a minimum total amount of undetectable errors in data vectors with set values of data and check vectors lengths. Importantly, the new sum code detects any double distortion in data vectors, which determines the prospects of its implementation for technical diagnostics problems. The article also compares the described systematic code with the classic code Berger. The article provides the results of tests with a set of MCNC Benchmarks reference combinational circuits for the organization of the concurrent error detection systems.
technical diagnostics, concurrent error detection systems, combinational circuit, code word, Berger code, weight-based sum code, data vector, error in data vector, structure redundancy
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