Two methods for synthesizing generators of modulo codes with summation of weighted transitions with a sequence of weight coefficients, which forms a natural series of numbers are described. The first is based on the use of a cascade structure consisting of three blocks (activating the transition, weighing the activated transition and obtaining the weight of the information vector), and then optimizing the last two blocks. The second is related to the use of the same cascade structure, but with a selective approach to adding weighting factors in the third block and corresponding simplification of the second block - it only has a cascade of activating transitions between bits and a weighting factor. Both methods are universal and can be used to synthesize generators of other weighted codes with summation, including codes with summation of weighted information bits. For such codes with the information vector length m, the generators can be obtained by removing the cascade of activation of transitions in the code generator with summation of weighted transitions with the information vector length m + 1.
concurrent error detection system, Berger code, code with summation, modulo code with summation of weighted transitions, tester, generator, complexity of the generator
1. Slabakov E. V. Samoproveryaemye vychislitel'nye ustroystva i sistemy (obzor) / E. V. Slabakov, E. S. Sogomonyan // Avtomatika i telemehanika. - 1981. - № 11. - S. 147-167.
2. Abramovici M. Digital System Testing and Testable Design / M. Abramovici, M. A. Breuer, A. D. Friedman. - New Jersey : IEEE Press, 1998. - 652 p.
3. Nicolaidis M. On-Line Testing for VLSI - A Compendium of Approaches / M. Nicolaidis, Y. Zorian // Journal of Electronic Testing : Theory and Applications. - 1998. - Vol. 12. - Issue 1-2. - Pp. 7-20.
4. Mitra S. Which Concurrent Error Detection Scheme to Shoose? / S. Mitra, E. J. McCluskey // Proceedings of International Test Conference. - USA, Atlantic City, New Jersey, 3-5 October 2000. - Pp. 985-994.
5. Rabochee diagnostirovanie bezopasnyh informacionno-upravlyayuschih sistem / A. V. Drozd, V. S. Harchenko, S. G. Antoschuk, Yu. V. Drozd, M. A. Drozd, Yu. Yu. Su- lima ; pod red. A. V. Drozda i V. S. Harchenko. - Har'kov : Nacional'nyy aero- kosmicheskiy universitet im. N. E. Zhukovskogo (HAI), 2012. - 614 s.
6. Parhomenko P. P. Osnovy tehnicheskoy diagnostiki (optimizaciya algoritmov diagnostirovaniya, apparaturnye sredstva) / P. P. Parhomenko, E. S. Sogomo- nyan. - M. : Energoatomizdat, 1981. - 320 s.
7. Theeg G. Railway Signalling & Interlocking - International Compendium / G. Theeg, S. Vlasenko. - Eurailpress, 2009. - 448 p.
8. Ubar R. Design and Test Technology for Dependable Systems-on-Chip (Premier Reference Source) / R. Ubar, J. Raik, H.-T. Vierhaus. - Information Science Reference, Hershey - New York: IGI Global, 2011. - 578 p.
9. Drozd A. V. Netradicionnyy vzglyad na rabochee diagnostirovanie vychislitel'nyh ustroystv / A. V. Drozd // Problemy upravleniya. - 2008. - № 2. - S. 48-56.
10. Sapozhnikov Val. V. Primenenie kodov s summirovaniem pri sinteze sistem zheleznodorozhnoy avtomatiki i telemehaniki na programmiruemyh logicheskih integral'nyh shemah / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efa- nov // Avtomatika na transporte. - 2015. - T. 1. - № 1. - S. 84-107.
11. Sapozhnikov Val. V. Samoproveryaemye diskretnye ustroystva / Val. V. Sapozhnikov, Vl. V. Sapozhnikov. - SPb. : Energoatomizdat, 1992. - 224 s.
12. Piestrak S. J. Design of Self-Testing Checkers for Unidirectional Error Detecting Codes / S. J. Piestrak. - Wrocław : Oficyna Wydawnicza Politechniki Wrocłavskiej, 1995. - 111 p.
13. Berger J. M. A Note on Error Detection Codes for Asymmetric Channels / J. M. Berger // Information and Control. - 1961. - Vol. 4. - Issue 1. - Pp. 68-73.
14. Jha N. K. A t-Unidirectional Errors-Detecting Systematic Code / N. K. Jha, M. B. Vora // Computers & Mathematics with Applications. - 1988. - Vol. 16. - N 9. - Pp. 705-714.
15. Efanov D. V. O svoystvah koda s summirovaniem v shemah funkcional'nogo kontrolya / D. V. Efanov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i telemehanika. - 2010. - № 6. - S. 155-162.
16. Das D. Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes / D. Das, N. A. Touba // Journal of Electronic Testing : Theory and Applications. - 1999. - Vol. 15. - Issue 1-2. - Pp. 145-155.
17. Das D. Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits / D. Das, N. A. Touba // Proceedings of 17th IEEE Test Symposium. - USA, California, 1999. - Pp. 370-376.
18. Das D. Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes / D. Das, N.A. Touba, M. Seuring, M. Gossel // Proceedings of IEEE 6th International On-Line Testing Workshop (IOLTW), Spain, Palma de Mallorca, July 3-5, 2000. - Pp. 171-176.
19. Saposhnikov Val. New Code for Fault Detection in Logic Circuits / Val. Saposhnikov, Vl. Saposhnikov // Proceedings of 4th International Conference on Unconventional Electromechanical and Electrical Systems. - St. Petersburg, Russia, June 21-24, 1999. - Pp. 693-696.
20. Mehov V. Concurrent Error Detection Based on New Code with Modulo Weighted Transitions between Information Bits / V. Mehov, Val. Saposhnikov, Vl. Sapozhnikov, D. Urganskov // Proceedings of 7th IEEE East-West Design & Test Workshop (EWDTW`2007). - Erevan, Armenia, September 25-30, 2007. - Pp. 21-26.
21. Mehov V. B. Kontrol' kombinacionnyh shem na osnove modificirovannyh kodov s summirovaniem / V. B. Mehov, Val. V. Sapozhnikov, Vl. V. Sapozhnikov // Avtomatika i telemehanika. - 2008. - № 8. - S. 153-165.
22. Sapozhnikov Val. V. Svoystva kodov s summirovaniem vzveshennyh perehodov s pryamoy posledovatel'nost'yu vesovyh koefficientov / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov, V. V. Dmitriev // Informatika i sistemy upravleniya. - 2014. - № 4. - S. 77-88.
23. Sapozhnikov Val. Optimum Sum Codes, that Effectively Detect the Errors of Low Multiplicities / Val. Sapozhnikov, Vl. Sapozhnikov, D. Efanov, V. Dmitriev, M. Cherepanova // RadioElectronics & Informatics. - 2015. - № 1. - Pp. 17-22.
24. Sapozhnikov Val. V. Sposob postroeniya koda s summirovaniem s uluchshennymi pokazatelyami obnaruzheniya oshibok v informacionnyh vektorah / Val. V. Sapozhnikov, Vl. V. Sapozhnikov, D. V. Efanov, V. V. Dmitriev, M. R. Cherepanova // Avtomatika na transporte. - 2016. - T. 2. - № 1. - S. 95-123.
25. Lala P. K. Principles of Modern Digital Design / P. K. Lala. - New Jersey : John Wiley & Sons, 2007. - 419 p.
26. Efanov D. V. Sposob sinteza generatorov vzveshennyh kodov s summirovaniem / D. V. Efanov // Izvestiya vysshih uchebnyh zavedeniy. Fizika. - 2016. - T. 59. - № 8/2. - S. 33-36.
27. Efanov D. V. K voprosu sinteza generatorov modificirovannyh kodov s summirovaniem vzveshennyh informacionnyh razryadov s posledovatel'nost'yu vesovyh koefficientov, obrazuyuschey natural'nyy ryad chisel / D. V. Efanov // Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitel'naya tehnika i informatika. - 2016. - № 4. - S. 13-26.
28. Sentovich E. M. SIS: A System for Sequential Circuit Synthesis / E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, A. Sangiovanni-Vincentelli // Electronics Research Laboratory, Depart- ment of Electrical Engineering and Computer Science. - University of California, Berkeley, 4 May 1992. - 45 p.
29. Wakerly J. F. Digital Design. Principles & Practices. - Prentice Hall, 1999. - 830 p.