Russian Federation
He article describes the process of synthesis of asynchronous JK fl ip-flops with different characteristics by using the fi nite automata theory. It reveals the disadvantage of a conventional implementations of asynchronous JK fl ip-flop, and then describes the synthesis of JK fl ip-flop without this disadvantage. The article presents four implementations of JK fl ip-flop as a fundamental circuit using Multisim software. During the implementation of the fl ip-flops in Multisim software few design features were considered, that are necessary for the correct operation of fl ip-flops. The article describes the operation of each option of JK fl ip-flops in the form of timing sheets. The timing sheets show the disadvantages of JK fl ip-fl op conventional implementations and the lack thereof in the synthesized fl ip-flops. The operation of 74LS107D fl ip-flop is simulated using Multisim software. The article also shows that the actual fl ip-fl op circuits do not have the described disadvantages.
Multisim, fi nite automaton, flip-flop, JK flip-flop, fl ip-flop synthesis, Multisim
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