Annotation:
For design of modern railway automation and remote control systems increasingly the microelectronics and microprocessor techniques are used, including field-programmable gate arrays (FPGA). This article describes an approach to the development of fault-tolerant automation systems with built-in concurrent error detection means. Concurrent error detection system is proposed to be formed on the basis codes with summation of on-bits. The article describes the characteristics of on-bit sum codes for detection of different types of errors at the outputs of the arithmetic logic units of FPGA.
Key words:
railway automation and remote control; reliability; safety; concurrent error detection (CED) system; sum codes; Berger code; modified Berger code; data bits; undetectable error.